Advanced semiconductor designs typically incorporate planarized multilevel structures including alternating layers of insulating materials supporting dual damascene and single damascene metal interconnections. Exemplary structures include alternating layers of insulating films, for example low-k dielectric films, with alternating chemical-mechanical hardmask endstop layers, for example silicon nitride and/or high density plasma oxide. Damascene metal can comprise, for example, copper.
Selective unlayering of these multilayer structures is often necessary for purposes of manufacturing rework or recovery of wafers, to perform defect yield analysis, and/or for electrical characterization or physical failure analysis of wafers, wafer fragments, individual dies, or packaged dies to perform reliability defect root cause analysis. Regular unlayering of these multi-layer structures can also be done in the course of automated pattern recognition inspection of defects in comparison with electrical test maps.
Unlayering multi-layer structures including low-k dielectric materials is problematic using known layer removal techniques. In particular, the fragile nature of the low-k dielectric materials cause them to react poorly to processes effective for oxides. For example, the lower modulus of low-k dielectric films are susceptible to damage when exposed to conventional chemical-mechanical polish processes. Wafer delayering for manufacturing rework or recovery of wafers cannot employ conventional delayering processes using plasma, or reactive ion etching or chemical-mechanical polish removal for planar deprocessing low-k films without damaging underlying films and undercutting metal layers. Still other techniques involving incident gallium ion beams can result in undesirable implantation of gallium into the low-k films or produce beam interactions (i.e. chemical bond breakdown in organic components present in some low-k films) producing unwanted electrical leakage paths and electrical shorts.
Further, conventional processes used to remove overlying metal layers, particularly copper single damascene and copper dual damascene metal, can result in damage to the underlying low-k dielectric layers. For example, conventional chemical-mechanical removal of copper layers can easily scratch, or embed polishing media or slurry into, underlying low-k films, by compromising hardmask endstop materials. Attempts to unlayer multilevel structures using conventional reactive ion etching can produce non-planar etch results due to the presence of porous regions within the low-k film as well as the in-homogenity of the low-k films, themselves.
Conventional reactive ion etching of copper requires elevated temperatures, producing nonvolatile species that can contaminate low-k dielectric films. Further, reactive ion etch removal of overlying insulating films can result in undercutting of underlying copper metal layers resulting in non-uniform etch removal of underlying low-k dielectric films.
New and improved processes are thus desirable which facilitate the selective planar de-processing of metal layers, hardmask materials and chemical-mechanical endstop materials over low-k dielectric films without damaging the underlying low-k dielectric layers.